1. Field of the Invention
The present invention relates to a digital level shifter circuit that has circuitry to reduce power dissipation or to block false transmission due to rapid changes in offset voltage.
2. Description of the Related Art
Digital level shift circuits typically translate a digital signal generated by a low voltage input power supply VDD to a digital signal that is offset from the low input voltage by a relatively high voltage which can change rapidly. The function of a digital level shifter is illustrated in FIGS. 1A and 1B, in which unshifted circuit 10 (FIG. 1A) can be compared to shifted circuit 12 (FIG. 1B).
In unshifted circuit 10, shown in FIG. 1A, voltage source 20 provides low voltage VDD across digital circuit 22, relative to ground. VDD can, for example, be any appropriate fixed voltage between 1V and 15V. Digital circuit 22 in turn provides a digital signal at its output (I/O) that switches between 0V and VDD, as shown in box 24.
In shifted circuit 12, shown in FIG. 1B, voltage source 30 similarly provides a digitally varying voltage VDDH across digital circuit 32, but is offset from ground by a level determined by an offset voltage source 34 connected between ground voltage from voltage source 30 and ground. Offset voltage source 34 is a fast, high voltage source that provides VOFFSET. As a result, digital circuit 32 provides a level shifted digital signal at I/O that switches between VOFFSET and VOFFSET+VDDH, as shown in box 36.
Integrated digital level shifters are typically implemented with a high voltage N-channel MOS device to shift signals from the low side to the high side. To shift in the other direction, a P-channel device is necessary.
Two main problems arise in integrated digital level shifters-power dissipation and false transmission due to fast changes in VOFFSET (also referred to as xe2x80x9cthe dv/dt problemxe2x80x9d).
In an integrated circuit (IC), VOFFSET can be as high as 1200V. Therefore, even if the high voltage level-shifting transistor sinks a relatively small current of only 1 mA when on, the power dissipation is 1.2 W, which is a large amount of power to be dissipated in an IC. This power dissipation problem has been solved in the past by transmitting only short pulses at signal transitions, level shifting these pulses and then using these pulses at the shifted voltage level to reconstruct the signal.
The dv/dt problem can be understood from FIG. 2, showing a high voltage level shift N-channel transistor 50 connected to an output signal line through resistor 52, having the value R. Transistor 50 has a parasitic capacitance 54 having the value C. Therefore, during the fast rising edge of VOFFSET transistor 50 passes a current IT=C*dv/dt. As a result, a pulse-like voltage VT=R*C*dv/dt will briefly develop across resistor 52. If VT exceeds the threshold voltage at which a transmitted signal is sensed, an error occurs.
To solve this dv/dt problem, three prior art solutions have been developed. The first solution is to use a pulse of current during transmission which is larger than the dv/dt current. However, for very fast dv/dt, such as 10V/nS, the required current would be so high that power dissipation would become impractical.
The second solution is to use a filter that cancels all shifting pulses having a duration less than a set value. This solution is based on the fact that if the derivative of VOFFSET is less than a certain value, the error current is limited and an error does not occur. If the derivative is greater than this value an error could occur, but its time duration is less than a time period of (dV/dt)*(VOFFSET(max)xe2x88x92VOFFSET(min)). The filter can, for example, cancel all pulses with duration less than this time period plus a protective incremental time. This solution has three main drawbacks: first, the time duration of a transmission impulse is so long that power dissipation is large; second, the error filter introduces delay even when the signal is good; and third, if the protective incremental time is not large enough, an error could be transmitted on slow dv/dt.
A third solution for the dv/dt problem is to use differential transmission. In this solution, the dv/dt error current is cancelled out as a xe2x80x9ccommon modexe2x80x9d signal on the drain of two identical level shift transistors, while a good signal provides current through only one transistor, and hence is a xe2x80x9cdifferentialxe2x80x9d signal.
The invention provides a new digital level shift circuit that alleviates the power dissipation problem. The new circuit includes feedback circuitry that obtains a feedback or xe2x80x9cacknowledgexe2x80x9d signal and, in response, turns off a level shifting device, limiting its on time. The acknowledge signal indicates that the device has made its output transition. As a result of this technique, power dissipation can be greatly reduced because the xe2x80x9conxe2x80x9d time of the level shifting device can be dramatically shortened.
The feedback circuitry can be implemented with a feedback device that provides the acknowledge signal by turning on when the level shifting device makes its output transition. One of the two devices can be an n-channel device and the other can be a p-channel device. For example, the devices can be high voltage NMOS and PMOS transistors.
In addition to reducing power dissipation, the timing of the acknowledge signal can change in a self-adaptive way in response to changes in transmission speed, such as from process or temperature change.
Also, the new circuit can be implemented without a filter, overcoming the problem of filter delay.
To alleviate the dv/dt problem, the digital level shift circuit of the present invention uses a differential circuit implemented with two p-channel devices and two n-channel devices and a transmission protocol that avoids simultaneous transmission by two transistors of the same channel type. The new circuit includes sense/prevent circuitry that senses when current greater than a threshold flows through both devices of one channel type, as would happen when dv/dt causes current to flow through the parasitic capacitances of both devices. In response, the sense/prevent circuitry prevents transmission. For example, the sense/prevent circuitry can prevent the devices of the other channel type from receiving their turn-on signals.
The sense/prevent circuitry can include sensing logic that can provide a prevent transmission signal only when current is flowing through the series resistances of both devices of one channel type. The sense/prevent circuitry includes prevent transmission logic that receives the prevent transmission signal and, in response, inhibits the devices of the other channel type from receiving turn-on signals.
The digital level shift circuit of the present invention with two n-channel and two p-channel devices further preferably includes control circuitry that controls when each device receives its turn-on signal. The control circuitry can include both feedback circuitry and sense/prevent circuitry as described above.
In a further aspect, the present invention avoids timing problems that could arise with the turn-on signals.
One timing problem could occur if the turn-on signal of a device is received while the sense/prevent circuitry is preventing transmission because dv/dt is above threshold. To avoid this problem, the sense/prevent circuitry can include, for each device, a storage element that stores a turn-on signal or transmission pulse until the prevent signal ends and the acknowledge signal of the device is received. This will not occur until the current due to dv/dt again drops below threshold.
A second timing problem could occur if one n-channel device and one p-channel device initiate transmission concurrently. To avoid this problem, the feedback circuitry can provide a scheme in which the acknowledge signal for each device of one channel type comes from one of the devices of the other channel type, but with none of the devices receiving its acknowledge signal from a device whose acknowledge signal it provides. For example, if the first and second n-channel devices are n1 and n3 and the first and second p-channel devices are p1 and p3, n1 can provide the acknowledge signal to p1, p1 to n3, n3 to p3, and p3 to n1.
Under this scheme, one of two concurrently transmitting devices will stop transmitting because it will receive a high signal from the other device, but the signal will be a transmission, not an acknowledge signal. To solve this further problem, the control circuitry can also include feedback detection circuitry for distinguishing acknowledge signals from transmissions. This makes it possible to restart a device that stopped transmitting in response to a transmission.
Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings.